The invention relates to an analog/digital converter.
EP-A-0 762 656 discloses an analog/digital converter which operates on the basis of the sigma-delta principle and is able to process a multiplicity of input signals in time-division multiplex mode. The converter contains a 1-bit analog/digital converter, a one-bit digital analog converter and also a single integrator circuit. A multiplicity of input signals are supplied to the integrator circuit via a multiplexer. The analog integrator circuit contains a multiplicity of capacitances in accordance with the multiplicity of input signals. The capacitances are connected indirectly between an input and an output of an operational amplifier. The output signal from the 1-bit digital/analog converter is fed back to the input of the integrator circuit with a delay. The delay by one period is in accordance with the two input signals of the circuit.
Analog/digital converters operating on the basis of the sigma-delta method produce a 1-bit data stream from a repeatedly oversampled analog input signal. A first-order sigma-delta analog/digital converter has a feedback structure in which the digital output signal is fed back to the negative input of an adder via a digital/analog converter. The adder subtracts the fed-back analog signal from the oversampled analog input signal, integrates the difference signal using an analog integrator circuit and converts the output signal from the analog integrator circuit into a digital output signal using a 1-bit analog/digital converter. nth-order sigma-delta analog/digital converters have n analog integrator circuits connected in series, with the feedback signal being routed to the input of each of the n integrator circuits.
xe2x80x9cThe Design of Sigma-Delta Modulation Analog-to-Digital Convertersxe2x80x9d, B. E. Boser, B. A. Wooley, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 1298-1308, December 1988 describes the basic principles of sigma-delta A/D conversion and shows, in FIG. 10, the circuit diagram for a second-order sigma-delta A/D converter which converts a differential analog input signal into a digital output signal.
xe2x80x9cA 14-Bit 80-kHz Sigma-Delta A/D Converter: Modeling, Design and Performance Evaluationxe2x80x9d, S. R. Norsworthy, I. G. Post, H. S. Fetterman, IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 256-266, April 1989 likewise shows, in FIG. 6, the circuit diagram for a second-order sigma-delta A/D converter. Since a sigma-delta converter has feedback and internal state memories and needs to reach a steady state in order to achieve a small conversion error, it is a difficult matter to process a multiplicity of input signals which are supplied to the converter in time-division multiplex mode.
U.S. Pat. No. 5,627,536 discloses a sigma-delta analog/digital converter for converting a multiplicity of signals supplied in time-division multiplex mode. Before each analog sample which is to be converted, the internal state memories of the converter need to be reset, and the converter needs to reach a steady state again in order to convert each sample. The disadvantage of this is that it reduces the conversion rate of the sigma-delta analog/digital converter.
The technical problem on which the invention is based is therefore that of specifying a sigma-delta analog/digital converter which is able to process a multiplicity of input signals supplied to the converter in time-division multiplex mode, where the conversion rate is not reduced by settling times of the sigma-delta analog/digital converter.
This problem is solved by a sigma-delta analog/digital converter having the features of patent claim 1. Advantageous refinements of the sigma-delta analog/digital converter can be found in the respective dependent claims.
An analog/digital converter has a multiplicity of integrator circuits, a 1-bit analog/digital converter and a 1-bit digital/analog converter. The multiplicity of analog integrator circuits are connected in series, and the 1-bit analog/digital converter is connected downstream of the last analog integrator circuit in the series. An output signal from the 1-bit analog/digital converter is supplied to the 1-bit digital/analog converter, and an output signal from the 1-bit digital/analog converter is subtracted from an input signal of each analog integrator circuit. A multiplicity of input signals are supplied via a multiplexer to the first analog integrator circuit from the analog integrator circuits connected in series, and each analog integrator circuit has a multiplicity of capacitances in accordance with the multiplicity of input signals. In this context, a respective capacitance from the multiplicity of capacitances can be connected between an output and an input of an operational amplifier in each analog integrator circuit, so that a feedback capacitance is formed. The output signal from the 1-bit digital/analog converter is delayed in accordance with the multiplicity of input signals. Advantageously, the multiplicity of capacitances in each analog integrator circuit form state memories. Each input signal from the multiplicity of input signals has an associated capacitance from the multiplicity of capacitances in each analog integrator circuit. The analog/digital converter can also be designed for differential input signals. In this case, each differential input signal from the multiplicity of differential input signals has two associated capacitances, so that each analog integrator circuit has, in total, twice as many capacitances as it does the multiplicity of differential input signals. Another advantage of the invention is the reduced circuit complexity for processing a multiplicity of input signals, since, instead of a multiplicity of sigma-delta analog/digital converters in accordance with the multiplicity of input signals, each analog integrator circuit is merely provided with a multiplicity of capacitances in accordance with the multiplicity of input signals in each case. This advantageously saves chip area when the sigma-delta analog/digital converter is integrated on one chip.
According to the invention, the output signal from the 1-bit digital/analog converter is delayed by a shift register, the shift register having a multiplicity of outputs in accordance with the multiplicity of analog integrator circuits. Each of the multiplicity of outputs is supplied to a respective input of one of the multiplicity of analog integrator circuits, so that the correct output signal from the 1-bit digital/analog converter is supplied to an analog integrator circuit.
According to the invention, the shift register is clocked by a clock signal which additionally clocks, in parallel, a multiplicity of sampling switches. Sampling switches are connected upstream of each analog integrator circuit, and the clock signal causes a respective capacitance from the multiplicity of capacitances to be connected between an output and an input of the operational amplifier in each analog integrator circuit. The clock signal thus controls the flow of conversion of the multiplicity of input signals.
In another particularly preferred embodiment, the multiplicity of outputs of the shift register are each delayed with respect to one another by one clock period of the clock signal. This means that signals associated with various input signals are present at each output of the shift register.
In one particularly preferred embodiment of the shift register, a first output from the multiplicity of outputs of the shift register is delayed by clock periods in accordance with the number of input signals reduced by one, and each further output from the multiplicity of outputs of the shift register is delayed by one respective further clock period.
In one particularly preferred embodiment, the multiplicity of capacitances in each analog integrator circuit have identical capacitance values. Integrated circuits advantageously allow the ratio to be set very much more accurately, in contrast with the absolute values of capacitances, and also the integration time period for each input signal is the same with identical capacitance values. In one preferred embodiment, the gain factor of each analog integrator circuit is determined by the ratio of a capacitance connected upstream of the input of the operational amplifier and a capacitance from the multiplicity of capacitances.
In one particularly preferred embodiment, the gain factor of each analog integrator circuit is 0.5.
In one preferred embodiment, the capacitance values of the multiplicity of capacitances in the first analog integrator circuit are larger than the capacitance values of the multiplicity of capacitances in the other analog integrator circuits.